20110329

Gigabit Ethernet transmission is currently unreliable for packets > 100 bytes and busted for > 200 bytes.

Things to try:

• Check CRC generation - there's some code that does this at http://www.edaboard.com/thread120700.html
  • CRC looks good!
• Fiddle with MTU on my computer (this shouldn't affect incoming packets, though!)
  • I really don't think this matters.
• Fiddle with code
  • I discovered a bug where EOF wasn't being transmitted, purely because I wasn't waiting the dst_ready signal before clearing it. This explains why very short packets worked. Unfortunately it now seems like the PHY isn't accepting any packets at all!
• Fiddle with timing constraints
  • Some clues at http://www.alteraforum.com/forum/showthread.php?t=3040 and possibly http://www.rcs.uncc.edu/wiki/index.php/Add_user_constraints_for_RGMII
  • Change the design to generate two 125 MHz clocks using the PLL. A 90 degree shifted one drives the GMII_TX_CLK pin. This should help with hold times, though the phase shift is arbitrary. Actually, I need a 270 degree clock as well, to drive the C1 clock of the OFDDRRSE.
  • Might be better to use an IODELAY2, though even that is a bit arbitrary due to a lack of calibration on the S6.