AEMB core

It's become apparent that using an Ethernet PHY and Wishbone is really the realm of a microprocessor. Try as I might, I can't get anything intelligent out of my PHY and everyone else is just using a soft core. Since I'm loosely basing my implementation on that of the USRP2, I'll use the same aeMB core as them!

• Download aeMB code from github, dump into the ISE proejct's ipcore_dir
• Add all of the rtl and sim files to the project, fiddle with implementation/simulation tags so that I'm not overwhelmed
• Wish there was an example application for it - the USRP2 code is pretty complex.
• Attempt simulation
  • To make life easier (hopefully), I'll use the GCC that comes with EDK. Start the EDK bash shell.
  • cd to the ipcore_dir/aemb/sw/
  • Run gccrom script. Fails due to missing main() reference. Why isn't there a makefile or anything useful like that?
  • Try this instead: ./gccrom c/aeMB_testbench.c. Fails due to an invalid pointer conversion.
  • Fix this by changing line 277 to alloc = (int *)malloc(8 * sizeof(int)); // allocate 32 byte
  • This works, but I don't have srecord, which is used to generate a vmem file.
  • Download and try to compile with mingw, which I have installed. Don't have the C++ compiler installed!
  • Reinstall mingw with C++ and more stuff. Re-run configure.. requires Boost.
  • Find another distribution that has Boost, but not libtool and no mingw-get. Give up!
  • Try again later with Cygwin. This totally works! I'm back on track!
  • Give up on simulation for now!
• Look at USRP2 implementation. An inferred block RAM is wrapped in a Wishbone interface and instruction and data caches.
• Just use the USRP2 bits for now!
• The USRP2 instruction RAM image is designed to be loaded using a CPLD - I just want to use it with a memory image file. Replace dpram32.v with a coregen?
  • stekern's orpsocv Atlys implementation of Openrisc uses MIG with Wishbone. Not sure I'll actually need megabytes of memory though!
  • The aeMB2 seems to implement its own instruction and data caches, whereas USRP has its own. Maybe it'd be better to use aeMB2? I wrote to the developers to ask if they had any advice on which top level to use.
    • The author says, "aeMB_edk32 is a single-threaded 3-stage pipeline core while the aeMB_edk62 is a dual-threaded 5-stage pipeline core. However, only the dual-threaded version is supported as the single-threaded version is deprecated."
  • Just wrapping the core generator in a Wishbone interface seems to be annoyingly tricky. Actually, it's not too bad!
• Finish doing that - attempt to compile test program, but even with some fiddling it's enormous (32 KB). Actually it's not - that's just the vmem file, which is a big ASCII one
• Actually, what the heck is an vmem file? It's a file that the Verilog $readmemh function can load, but does that work with BRAMs? Coregen wants a coe file.

Simulation

Let's try simulating sim/verilog/edk62.v

• Get rid of the aeMB_* files, add all of the aeMB2_* ones.
• Add sim/verilog/edk62.v
• Modify $readmemh lines to include the path of the vmem file.
• Run!
• It looks like it's retrieving the first word from iram, which according to rom.dump is the location of the start of the program.
• It then tries to retrieve data from iram[1], which is undefined, and stops.
• Possibly a mis-match between the EDK compiler and the aeMB compiler? Let's try replacing the first few instructions with NOPs.. or something like an or r0,r0,r0 (0x80000000)
• This doesn't help either! It doesn't look like it's actually trying to jump to an invalid address or anything.
• Trace to three undefined signals in aeMB2_ctrl.v line 207 - ask author for clarification on these.
• Author suggests using sim/verilog/edk63.v instead, and the testbench.cc.
• This seems to work far better! The code uses iprintf() calls and it's not clear if isim supports these, but I'll dig a bit more.

Other ideas:

• Just buy the EDK! ~$500
• I could use Lattice Mico32, which has Wishbone and SPI (and a TEMAC, though it's not free either) - couldn't see any really easy guides for using it with ISE, though.