GMII interface notes

I wanted to add a GMII (gigabit Ethernet) interface using the Marvell 88E1111 MAC on the Digilent Atlys. The standard solution is to use Xilinx's TEMAC core, but this requires an EDK license ($500). Sod that! Instead, I adapted some GPLed code from the USRP2, which does a similar thing to what I'm trying to do anyway.

• Create test project, import in simple_gemac.v and the two main test benches, then every required module, one by one
• Recreate the FIFO cores using the latest version of the Coregen wizard. This required a manual examination of the .xco file because ISE refused to do anything with the core generated for a different FPGA.
• Modify the simple_gemac_wrapper_tb.v so that it could send packets from a file (like the simple_gemac_tb.v)
• Gradually come to understand the system a bit
• Implement a state machine to send out small test packets
• Test on the Atlys

So far it synthesises but doesn't work! I have to head out in a minute, but it can't be too far off.

Took nearly a whole week to figure out, but the 88E1111's reset is active low! Ugh.

It'd be nice to package this up (since it's 99% GPL code anyway) and make it available to other people who want to do this, since there's limited information on how to do this without the EDK. Things on Opencores generally look comprehensive but have almost no documentation on how they work and how to use them!

The MAC most likely needs some configuration registers tweaked. I can figure this out based on the Digilent EDK example and possibly the Linux driver for it. http://www.chokladfabriken.org/projects/orpsoc-atlys may have some hints, though at first glance the included Ethernet core is only 10/100.

Start peeking and poking the registers by manipulating the WB bus. This would be loads easier with a processor!

Atlys has the following config pin setup:

• CONFIG[0] = VCC2V5 = 000 = PHYADR[2:0]
• CONFIG[1] = GND = 111 = { ENA_PAUSE, PHYADR[4:3] }
• CONFIG[2] = VCC2V5 = 000 = { ANEG[3:1] }
• CONFIG[3] = VCC2V5 = 000 = { ANEG[0], ENA_XC, DIS_125 }
• CONFIG[4] = VCC2V5 = 000 = { HWCFG_MODE[2:0] }
• CONFIG[5] = VCC2V5 = 000 = { DIS_FC, DIS_SLEEP, HWCFG_MODE[3] }
• CONFIG[6] = LED_RX = 010 = { SEL_TWSI, INT_POL, 75-50OHM }; // MDC/MDIO enabled

Based on phy_utils.c in the BIST, need to set the following for ANEG:

Register 0 bits 12, 8 and 6 should be 1 Register 0 bit 13 should be 0 Register 4 bits 8,7,6 and 5 should be 1 Register 9 bits 9 and 8 should be 1 Register 9 bits 12, 11 and 10 should be 0 Register 16 bits 6:5 should be 1

(though I don't really care about ANEG)

And:

ENA_XC = 1
DIS_125 = 1
HWCFG = 1111
DIS_FC = 1
DIS_SLEEP = 1
INT_POL = 1
Ohm_75_50 = 0

20110228 progress

I've now programmed the HWCFG mode and fixed a problem in the state machine (an incorrect next state assignment - urgh! It'd be nice if xst could be configured to give a terminal error for this) and the board is now spewing forth an endless stream of malformed packets!